amp inc’s 2.5″ PATA interface solid state storage drives adopts advanced SSD controller and NAND Flash components. It is compatible with ATA-7 protocol and supports PIO-4, MWDMA-2 and UDMA-6 transfer rates. The SSD supports mainstream OS, such as Windows/ MAC/ Linux/ Unix/ Solaris/ Vxworks, and provides storage capacity ranging from 8GB to 128GB. It is widely used in the reinforcement computer, industrial control computer, embedded computer and national defense fields.
amp inc’s 2.5″ PATA interface solid-state drives carry out a series of strict temperature, vibration and shock tests in accordance with the standards of military equipment to make sure the products work in harsh environments.
MLC
C = Commercial Temperature |
SLC
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Typical Applications:
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Key Features (Flash Management):
- Advance Wear-Leveling Algorithm The NAND flash devices are limited by a certain number of write cycles. When using a file system, frequent file table updates is mandatory. If some area on the flash wears out faster than others, it would significantly reduce the lifetime of the whole device, even if the erase counts of others are far from the write cycle limit. Thus, if the write cycles can be distributed evenly across the media, the lifetime of the media can be prolonged significantly. The scheme is achieved both via buffer management and specific advanced wear leveling to ensure that the lifetime of the flash media can be increased,
and the disk access performance is optimized as well. - S.M.A.R.T Function S.M.A.R.T. is an acronym for Self-Monitoring, Analysis and Reporting Technology, an open standard allowing disk drives to automatically monitor their own health and report potential problems. It protects the user from unscheduled downtime by monitoring and storing critical drive performance and calibration parameters. Ideally, this should allow taking proactive actions to prevent impending drive failure. SMART feature adopts the standard SMART command B0h to read data from the drive. When the SMART Utility running on the host, it analyzes and reports the disk status to the host before the device is in critical condition.
- Built-in Hardware ECC The ATA-Disk Module uses BCH Error Detection Code (EDC) and Error Correction Code (ECC) algorithms which correct up to eight random single-bit errors for each 512-byte block of data. High performance is fulfilled through hardware-based error detection and correction.
Specifications:
Physical Specifications | Interface | 44-pin IDE |
Dimension | 100.20mm x 69.85mm x 9.3mm | |
Capacity | 8GB-256GB | |
Flash Media | MLC-NAND Flash 8GB-256GB SLC-NAND Flash 8GB-256GB |
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Performance | Sequential Read | Up to 80 MB/s |
Sequential Write | Up to 40 MB/s | |
4KB Random Read | Up to 3800 IOPS | |
4KB Random Write | Up to 375 IOPS | |
Reliability | Wrtie endurance: 8 years@ 100G write/day(32G) Read endurance: unlimited MTBF: >2,000,000 hours Date retention: >20years@ 25°C Date destroy do not support Sudden power-off recovery support ECC: 8bits for 512Bytes S.M.A.R.T and dynamic power management support Bad block management algorithm |
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Environment | Storage temperature: -55˜95°C Operation temperature: Optional Humidity: 5%˜95% Vibration: 20G Peak, 10~2000Hz, (15mins/ Axis) x3 Axis Shock: 1500G (@0.5ms half sine wave) |
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Electrical Specifications | Input Voltage | 5V ± 5% |
Read Current | Read = 1.6 W (Max) | |
Write Current | Write = 2.4 W (Max) | |
Idle Current | Idle = 1.2 W | |
Host Interface | Compliant with ATA-7 specification | |
Supports PIO Mode 0-4 | ||
Supports Multi-Word DMA Mode 0-2 | ||
Supports Ultra DMA Mode 0-6 | ||
Operating Temperature | Commercial Grade ( 0°C+70°) Industrial Grade ( -40°C+85°) |
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Weight | < 120g |
Performance, power consumption and weight vary with different capacity of products.
Materials Composition:
Case: | Anodized aluminum |
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Connector: | Phosphor bronze/gold (contact), Nylon 6T (insulator) |
PCB: | Glass cloth & paper Copper Cyanoguanidine Diethylene glycol monoethyl Ether acetate Barium Sulfate Silicone Epichlorhydrin-bisphenol A Resin, Barium sulfate Titanium dioxide Nickel, gold |
Device Certifications:
Certification/Compliance | Description |
CE Compliant | Indicate conformity with the essential health and safety requirements set out in European. Directives Low Voltage Directive and EMC directive. |
FCC Certified | Federal Communications Commission Certified |
RoHS Compliant | Restriction of Hazardous Substance Directive |
UL Compliant | 94V-0-1 |
Electrical Requirement:
Operating Range
Range | Ambient Temperature | Input Voltage |
Commercial Temperature | 0° to +70° | 4.75V ˜ 5.25V |
Industrial Temperature | -40° to +85° |
Absolute Maximum Rating
Caution: Absolute Maximum Stress Ratings- Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.
Absolute maximum power pin stress ratings
Parameter | Symbol | Conditions |
Input Power | VDD | -0.3V min to 6.5V max |
Voltage on any pin except VDD with respect to GND | V | -0.5V min to VDD +0.5V max |
Power Specification:
Recommended DC operation voltage: 4.75 ˜ 5.25V
Parameter | Typical | Unit | |
Standby | 0.5 | W | |
Idle | 0.3 | W | |
4KB sample data | Sequential read | 1.2 | W |
Sequential write | 1.5 | W | |
Random read | 1.2 | W | |
Random write | 1.7 | W | |
512KB sample data | Sequential read | 1.05 | W |
Sequential write | 1.6 | W | |
Random read | 1.05 | W | |
Random write | 1.65 | W |
PATA SSD Block Diagram:
2.5″ PATA Physical Characteristics:
Physical Dimensions
Interface Diagram
Jumper Setting
Pin Assignment
Pin | PATA-ATA | Pin | PATA-ATA |
1 | RESET# | 23 | HIOW# |
2 | GND | 24 | GND |
3 | D7 | 25 | HIOR# |
4 | D8 | 26 | GND |
5 | D6 | 27 | IORDY |
6 | D9 | 28 | CSEL# |
7 | D5 | 29 | DMACK# |
8 | D10 | 30 | GND |
9 | D4 | 31 | INTRQ |
10 | D11 | 32 | IOCS16# |
11 | D3 | 33 | A1 |
12 | D12 | 34 | PDIAG# |
13 | D2 | 35 | A0 |
14 | D13 | 36 | A2 |
15 | D1 | 37 | CS1FX# |
16 | D14 | 38 | CS3FX# |
17 | D0 | 39 | DASP# |
18 | D15 | 40 | GND |
19 | GND | 41 | VCC |
20 | KEY | 42 | VCC |
21 | DMARQ | 43 | GND |
22 | GND | 44 | NC |
23 | TRIG | B | CSEL |
C | M/S | D | PSEL |
Signal Description
Signal | Pin | Type | Description |
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A2-A0 | 36,33,35 | I | A[2:0] are used to select one of eight registers in the Task File. |
CS1FX#,CS3FX# | 37,38 | I | CS1FX# is the chip select for the task file registers. CS3FX# is used to select the alternate status register and the Device Control register. |
CSEL# | 28 | I | Cable select. |
D15-D0 | 18,16,14,12,10,8,6,4,3,5,7,9,11,13,15,17 | I/O | D[15:0] Data bus |
IOCS16# | 32 | This output signal is asserted low when the device is indicating a word data transfer cycle. | |
DMACK# | 29 | I | DMA Acknowledge – input from host |
DASP | 39 | I/O | The Drive Active/Slave Present signal in the Master/Slave handshake protocol. |
DMARQ | 21 | O | DMA Request to host |
GND | 2,19,22,24,26,30,40,43 | – | Ground |
INTRQ | 31 | O | This signal is the active high Interrupt Request to the host. |
IORDY | 27 | I | Unused |
IORD# | 25 | I | This is an I/O Read strobe generated by the host. This signal gates I/O data onto the bus from the chip. |
IOWR# | 23 | I | The I/O Write strobe pulse is used to clock I/O data into the chip. |
KEY | 20 | – | Key to connecter |
PDIAG# | 34 | I/O | The Pass Diagnostic signal in the Master/Slave handshake protocol. |
RESET# | 1 | I | This input pin is the active low hardware reset from the host. |
VCC | 41,42 | – | Power Supply, 5V |
A | TRIG | I | Intelligent trigger input |
B | CSEL | I/O | Cable select |
C | M/S | I | Master/slave configuration |
D | PSEL | I | Master/slave |
Software Interface:
ATA Command Set
This section defines the software requirements and the format of the commands the host sends to the PATA SSD. Commands are issued to the SSD by loading the required registers in the command block with the supplied parameters, and then writing the command code to the Command register. The manner in which a command is accepted varies.
Command Name | Code | PARAMETERS USED | |||||
C | SN | CY | DR | HD | FT | ||
CHECK POWER MODE | E5h | X | X | X | O | X | X |
EXECUTE DIAGNOSTICS | 90h | X | X | X | O | X | X |
FLUSH CACHE | E7h | X | X | X | O | O | X |
FLUSH CACHE EXIT | EAh | X | X | X | O | O | X |
IDENTIFY DEVICE | ECh | X | X | X | O | X | X |
IDLE | E3h | O | X | X | O | X | X |
IDLE IMMEDIATE | E1h | X | X | X | O | X | X |
INITIALIZE DEVICE PARAMETERS | 91h | O | X | X | O | O | X |
READ DMA | C8h or C9h | O | O | O | O | O | X |
READ DMA EXT | 25h | O | O | O | O | O | X |
READ FPDMA QUEUED | 60h | O | O | O | O | O | O |
READ LOG EXT | 2Fh | O | O | O | O | O | O |
READ MULTIPLE | C4h | O | O | O | O | O | X |
READ MULTIPLE EXT | 29h | O | O | O | O | O | X |
READ SECTOR(S) | 20h or 21h | O | O | O | O | O | X |
READ SECTOR(S) EXT | 24h | O | O | O | O | O | X |
READ VERIFY SECTOR(S) | 40h or 41h | O | O | O | O | O | X |
READ VERIFY SECTOR(S) EXT | 42h | O | O | O | O | O | X |
RECALIBRATE | 10h | X | X | X | O | X | X |
SECURITY DISABLE PASSWORD | F6h | X | X | X | O | X | X |
SECURITY ERASE PREPARE | F3h | X | X | X | O | X | X |
SECURITY ERASE UNIT | F4h | X | X | X | O | X | X |
SECURITY FREEZE LOCK | F5h | X | X | X | O | X | X |
SECURITY SET PASSWORD | F1h | X | X | X | O | X | X |
SECURITY UNLOCK | F2h | X | X | X | O | X | X |
SEEK | 7xh | X | X | O | O | O | X |
SET FEATURES | EFh | O | X | X | O | X | O |
SET MULTIPLE MODE | C6h | O | X | X | O | X | X |
SLEEP | E6h | X | X | X | O | X | X |
Smart Command Support
D0h | Read Data | D5h | Read Log |
D1h | Read Attributer Threshold | D6h | Write Log |
D2h | Enable/Disable Auto save | D8h | Enable SMART Operations |
D3h | Save Attribute Values | D9h | Disable SMART Operations |
D4h | Execute OFF-LINE Immediate | DAh | Return Status |
AMP Inc. reserves the right to change products and specification without notice.