The purpose of this white paper is to explain what wear leveling is and how it can help increase the life expectancy of amp inc’s compact flash when use in conjunction with error correction. Due to the nature of NAND flash, wear is inevitable when writing to a NAND flash. With wear leveling, the write patterns to a NAND flash is more evenly distributed thus increasing its life expectancy.
Types of NAND Flash
There are two types of NAND flash that are currently on the market: SLC and MLC. amp inc only uses SLC on all its compact flash products. SLC flash is 10 times more durable than MLC flash. The erase/write cycle for an SLC NAND flash is 100,000 cycles when use with one-bit ECC.
A brief discussion about the architecture of NAND flash is necessary in order to understand how wear leveling is implemented.
NAND flash is divided into physical blocks, these blocks are further divided into sectors. Writing to a NAND flash is accomplished per sector, erasing involves per block. Physical blocks are group into zones. Each zone has approximate 3% spare blocks beyond what is logically assigned to the meet the total capacity of the compact flash. These spare blocks are used during the wear leveling operation.
When data is written to NAND flash, it is written to its logical address as far as the host is concern. It is this translation that allows wear leveling to be successful.
If a same data is written to the same logical address of the NAND flash, the compact flash controller re-maps the data to the spare blocks, thus preventing the data from being written to the same physical location of the NAND flash but without changing the logical address of the data. amp inc employs dynamic wear leveling which is wear leveling performs on changing or dynamic type of data and not static data such as operating system. With this type of wear leveling, it is best to have an operating system of small size as possible so that more spare blocks are available for wear leveling. Therefore, a reliability of a compact flash with wear leveling can be estimated by using the formula below.
Endurance(years) = (C – D)*E*(1 – M)
C = Card capacity, in MB
D = Amount of static data, e.g. operating systems, in MB
E = Erase /write cycle of NAND flash
M = Design safety margin
S = File size that is being written, in MB
f = frequency of writes, in per minutes
A 2GB with an operating system of size 300MB writing a file size of 0.5MB at a rate of 30 writes/minutes with a 5% safety margin will have an endurance of:
Endurance(years) = (2048MB-300MB)*100,000(1-0.05)
= 21.06 years
Error Correction Code
It is normal for a compact flash (CF) to encounter errors during reading as part of its standard operation. The basis of all error detection and correction is the inclusion of redundant information and special hardware (CF controller) and software (firmware) to use it. Each sector of the CF contains 512 bytes or 4,096 bit of user data. In addition to these bits, additional bits (2 bit) are added to the implementation of error correction. These bits contain information about the data that can be used to correct errors encountered during accessing the real data. When writing to a sector of a compact flash, the appropriate correction code is generated in the bit preserved for that particular sector. When the sector is read back, the user data combine with the correction code will tell the compact controller if any errors occur during the read. Errors encountered will be corrected before passing the data to the host’s system. This is done ‘on the fly’ with no intervention from the user and no degradation in performance.
In summary, wear leveling combines with error correction code increase the reliability and durability of a compact flash dramatically. The above information is provided as a guide only and will vary from systems to systems due to application and usage differences.